J'ai postulé en ligne. Le processus a pris 12 mois. J'ai passé un entretien chez Intel Corporation (Washington, DC) en mai 2024
Entretien
Experienced professional as SoC Design Engineer with expertise in GPU architecture, SoC globals including Clocking, reset, low power design and chassis components. STA, system verilog, SoC clock architect for Intel's Alchemist and Battlemage GPU.
Micro architect for SoC globals including clocking, reset, low power, registers and debug networks.
Questions d'entretien [1]
Question 1
1. what are inertial delay and transport delay?
2. Circuit using D latch, master slave FF & explain it
3. how u will reduce the input frequency? draw the circuit & explain
4. D FF Verilog code
Walk-in in KL. Was interviewed by senior engineer from my team. Questions mostly about what i include in my resume and electrical question and basic programming. How transistor works and was asked to draw logic circuit base on the requirements.
Questions d'entretien [1]
Question 1
How transistor works and design logic circuit base on a problem given ?
1 technical round 1 hr duration..... Was on campus placement.... It went good.. They started with basics and went deeper... And to crack intel interviews u must answer every question they ask and that should match with their expected answers.... Also they shall ask logocal, critical and situation based question... So be prepared
J'ai passé un entretien chez Intel Corporation (Cartago)
Entretien
The hiring manager scheduled a meeting to interview me and know more about me and my abilities, explain me about the job, what I eventually will going to do and things like these
Questions d'entretien [1]
Question 1
Tell me about your experience with the VLSI design