Mosfet modes, NOr gate logic, interconnect delay, RC delay, logic design using de-morgans, diff between nand and nor gates, diff between latches and FFs.

Phone screen: difference between FF and latch, charge sharing dynamic logic circuits, Which is faster pmos or nmos and why, driver in one end and receiver at the other end separated by transmission wire how would you design? ( ie pi model ), how would you design AND gate using NOR, MOSFET characteristics ( Saturation, cut off) Onsite - 9am-10am : Manufacturing Test Environment 10-11am: ATPG-based test content & debug 11am-noon: Functional Content Development & Validation 1:15-2:30pm: Silicon debug & triage 2:30-3pm: Technical Q&A