J'ai postulé via un recruteur. Le processus a pris 2 semaines. J'ai passé un entretien chez Xilinx (Dublin, Dublin) en févr. 2017
Entretien
The interview was in depth and I was asked to write some hdl code. They will also often answer non work related "trick" questions to test your problem solving skills. They will push your limits which is not surprising from an industry leader.
Questions d'entretien [1]
Question 1
HDL related questions at start, then ones related to timing constraints and clock domain crossing and how you would solve different scenarios.
J'ai postulé via la recommandation d'un employé. Le processus a pris 3 jours. J'ai passé un entretien chez Xilinx (Campbell, CA) en févr. 2014
Entretien
Phone Screen -> In Person (Half Day) interview with several different people (1 at a time). Some guys asked me to describe a module I had worked on. Some guys asked me about PCIE flow control, transaction ordering. This was an interview with the iP team designing the hard-core IP sections of the FPGAs. Specifically the PCIE group.
Questions d'entretien [1]
Question 1
Most difficult was how would you write a script to calculate the latency of a PCIE bus given a data base of several transactions, and their completions.
An easier one that was asked that was unexpected, given I am more HW is: Write a function to detect a one-hot encoded state variable. I sort of bombed it at the interview, but looked into the solution in detail after the interview.
J'ai postulé via une autre source. J'ai passé un entretien chez Xilinx (Hyderâbâd) en avr. 2013
Entretien
Four telephonic rounds, Four face to face technical rounds , one Hiring manager formal discussion and one HR formal discussion.
All were deep into technical details. Everybody checked project executed and technical expertise on full execution. Fundamental of Digital Electronics.
