#Telephonic Round: Simple digital, verilog, timing Qs (30mins) #Onsite Interview:(45 mins each) Round 1: Simple Digital Qs, Verilog code (Case , if-else difference, Blocking-Nonblocking difference, Unintensional latch problem), Power reduction techniques(Clk Gating) + extended Qs on same topic Previous work related Qs , Module's overall working Round 2: Verification basics like: What is fork -Join? Tasks and fns Pass by value , Pass by Refn Logic behind Linked list entry removal(How address pointer is changed) Round 3: Verilog code for shift left, shift right, parallel load functionality Some logical puzzales Digital concepts like basic gates using Mux, Gate Reduction etc. Round 4 More on Power reduction Setup and Hold time eqs and Violation removal techniques Diffn betn: Glich and Jitter and skew