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      Entretien pour Digital Design Engineer

      17 mai 2017
      Candidat à l'entretien anonyme
      New Delhi

      Autres retours d’entretien d’embauche pour un poste comme Digital Design Engineer chez Texas Instruments

      Entretien pour Digital Design Engineer

      27 janv. 2026
      Employé (anonyme)
      Offre acceptée
      Expérience positive
      Entretien moyen
      Aucune offre
      Expérience négative
      Entretien moyen

      Candidature

      J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 1 jour. J'ai passé un entretien chez Texas Instruments (New Delhi) en août 2016

      Entretien

      They conducted a written test in which a good 30% students for shortlisted for Analog Engineer and Digital Engineer. Cutoff was 40% marks. We heard that they had a good number of vacancies that year. Interview was average and they ask about your favourite topics and then start quizzing. There were 2 technical interview rounds followed by HR round. However, I reached till the final technical round (which lasted some 55 minutes), another student (who was the last person to be interviewed) went in. Interview started for this guy. But when I came out of the interview cabin, the results were already declared! (TI-BANGALORE DID NOT CONSIDER MY INTERVIEW AND OBVIOUSLY THAT GUY'S INTERVIEW TOO). The biggest irony is that, that guy was still being interviewed when the new recruits were celebrating outside! We were made a fool just to be in waiting for 4 long hours. And after the wait was over, they had already made up their mind to recruit among the students who interviewed before us ... Shocking! Unexpected from TI! Hope they were more responsible

      Questions d'entretien [1]

      Question 1

      Round 1:- Logic Families, Mux, Demux, In CMOS circuits, which among tphl and tplh is longer? And why? Divide-by-3 counter, Round 2:- (after a wait of the futile 4 hours) Significance of 'reset' signal in digital circuits Given a step input to a low pass filter, high pass filter and band pass filter respectively, what do you expect the output to look like? Dissimilate a square wave into its harmonics (this question because I had mentioned signal processing projects in my resume) Now a days we have a large number of cells in logic blocks? What do you think is the approach to detect an error in such a case?
      1 réponse

      Candidature

      J'ai passé un entretien chez Texas Instruments

      Entretien

      Basic digital design, clock domain crossing ,fifo for analog prepare rc circuit. keep your basic clear and dont try to make interviewer fool. Approach to problem is checked rather than answers.

      Questions d'entretien [1]

      Question 1

      fifo depth, multiplier, 2s compliment rounding off
      Répondre à cette question

      Entretien pour Digital Design Engineer

      22 sept. 2025
      Employé (anonyme)
      Thiruvananthapuram
      Offre acceptée
      Expérience positive
      Entretien difficile

      Candidature

      J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 2 jours. J'ai passé un entretien chez Texas Instruments (Thiruvananthapuram)

      Entretien

      They started with asking questions about my projects in the resume. And they went deep into it. Next they asked what is your favourite subject for which I answered digital electronics. They asked about fsm, flip flops, timing etc.

      Questions d'entretien [1]

      Question 1

      Draw the transient response of the given circuit
      1 réponse

      Entretien pour Digital Design Engineer

      15 août 2025
      Employé (anonyme)
      Dallas, TX
      Offre acceptée
      Expérience neutre
      Entretien moyen

      Candidature

      J'ai passé un entretien chez Texas Instruments (Dallas, TX)

      Entretien

      Had 2 rounds of technical interviews and 1 round of behavioral interview. As long as you know your basics of digital logic, such as counters, muxes, STA, etc it's not that hard.

      Questions d'entretien [1]

      Question 1

      Design a 2 DFF synchronizer.
      Répondre à cette question