Interview process borders on abuse and is clearly designed to get free work out of applicants. I put 35+ hours into a Verilog design problem that would have taken 4 times that to complete. Only to have them come back with factually false claims that they found bugs in my solution that were not actually bugs. I spoke to absolutely no one with any engineering competence whatsover.

1 screening, 1 coding assessment, final round in person with various 1:1's digital design UVM question. HR moved very quickly and everything was within a month. Friendly staff however the final interview was quite challenging since i did not know about packet protocols.