in design verfication there are 3 rounds 1st one is written and 2nd techinical interview they ask about basic of digital design , verilog, system verilog, basic of uvm and 3rd is hr round
J'ai postulé via une autre source. Le processus a pris 1 jour. J'ai passé un entretien chez Shiva (Bengaluru) en mai 2024
Entretien
1st round Written test-Test is based SV and UVM
2nd round based System Verilog and UVM and Assertions
3rd round based Project and UVM and Constraints, Functional coverage and Code coverage.
Questions d'entretien [1]
Question 1
What is the difference between function new and create constructor
2 rounds of interview technical and hr round in technical round they have asked basic questions I tried to answer every question some I even don't know that topic exist
Questions d'entretien [1]
Question 1
Questions like blocking assignment and non blocking assignment difference
