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      Entretien pour ASIC/FPGA Verification Engineer

      19 févr. 2014
      Candidat à l'entretien anonyme
      Castle Rock, CO
      Offre refusée
      Expérience négative
      Entretien moyen

      Candidature

      J'ai postulé en ligne. Le processus a pris 6 semaines. J'ai passé un entretien chez FirstPass Engineering (Castle Rock, CO) en août 2013

      Entretien

      I found this job opportunity by searching "Colorado FPGA job." I emailed my resume to the address listed on their website. A week later, I got an email response requesting that I complete the attached "prescreen questionnaire" and employment application. The questions were as follows" 1. How do you configure your favorite text editor for code development? 2. What Linux shell was your last executed shell script run under? What was the script 3. doing? Did you author this or other related scripts? 4. Do you Perl? Do you TCL? 5. What is your preferred source control (or configuration management) tool? Do you use it in command line mode? 6. Have you performed requirements traceability? Where in the development process did these requirements trace down to? 7. Describe a buffering scheme generally associated with strict-order data flows Describe for out-of-order data flows. 8. Roughly how many hand-coded RTL modules have you authored in the past two years? 9. Have you authored a hand-coded RTL module that manipulates I and Q components? 10. Describe your level of expertise (low/medium/high) within each of the following four test environments: Standard VHDL/Verilog/System Verilog directed test; SV-AVM; SV-OVM; SV-UVM 11. Briefly describe a recent usage example of the application of a constrained random technique. 12. Do you differentiate synthesis constraints from STA constraints? Why (or why not)? 13. How do you feed constraints into your STA tool? 14. Briefly summarize a critical path group of a recent design. What was your setup slack? 15. Have you performed design floorplanning? What were your objectives and strategy? After I returned the questionnaire and application, I was scheduled for a phone interview. In all, there were three phone interviews. Two of the phone interviews where with the program manager. The other phone interview was with a group of engineers. After the phone interviews, I was scheduled for an in-person interview. The in-person interview was an all day where I met several technical employees at the company. The in-person interview was a mixed-bag. A few of the interviewers had not reviewed my resume or the pre-screen questionnaire before the interview. One interviewer even exclaimed, "I didn't even know we had this questionnaire!" Another interviewer had a very hard time communicating his questions and got frustrated when I could not answer his ill-composed questions.

      Questions d'entretien [1]

      Question 1

      FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.
      2 réponse(s)
      4