J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 2 jours. J'ai passé un entretien chez Cadence Design Systems (Pune) en oct. 2024
Entretien
Round 1: Written Test
--> 7 subjective questions were asked.
Particular Topics:
1) 2 on Verilog(HDL for JK FF with set and reset) and one was based on instantiation of module)
2) 1 on STA
3) 1 on FSM( detect 11001 and 11011 simultaneously with overlap)
4) 1 on CMOS function Implementation with sizing of transistors(using Euler Path)
5) Frequency divider( divide by 3, with 50% duty cycle)
6) HDL was given, and they asked to make a hardware implementation of it
Round 2: Interview
--> It went about 55 minutes.
Questions d'entretien [4]
Question 1
Questions starting from CMOS Inverter, its VTC, what will happen if we replace NMOS with a resistor(effect on output swing and VTC), what are unity gain points on VTC(Vil and Vih), and what is their use(basically to define Noise Margins).
Then, the interviewer deep-dived into ASIC Design Flow( he asked many questions on Post RTL phase{synthesis, routing, clock trees, placement, STA, Layout, etc..}.
J'ai postulé en ligne. J'ai passé un entretien chez Cadence Design Systems (Cambridge, East of England, England)
Entretien
It was a 30-minute interview that was primarily focused on technical skills. I was also asked to give a 10-minute presentation on a verification-related project.
The interview was engaging and enjoyable. The interviewer's had over 20 years of industry experience and demonstrated deep technical knowledge. The discussion was insightful, and I appreciated the opportunity to interact with someone with such extensive expertise.
Overall, it was a positive experience with a strong focus on technical understanding and practical verification concepts.
Questions d'entretien [1]
Question 1
They asked questions me on the AMBA Protocols [AHB/APB]
Asked me questions on Linting, blocking, non-blocking, FSM and about verification environment,
J'ai postulé en ligne. Le processus a pris 1 semaine. J'ai passé un entretien chez Cadence Design Systems (Cork) en mars 2026
Entretien
This was a interview for a intern position for a digital logic design role
1. HR call to setup interview
2. Technical Round with Hiring Manager
3. Behavioral Round with another Manager
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Cadence Design Systems (Pune) en févr. 2026
Entretien
1 screening,2 tech and 1 HR. Technical easy-medium. Focus on core programming and puzzle type questions.
Only move on to the tech interview if 5min screening goes well so make sure your resume stands out.
