Asked about projects on my resume. And then technical questions:
1,mismatching in layout: Prov is one contributor. (glitch?)
2,how to decrease power, dynamic and static (sub threshold), Why can use CMOS
3,logic design: change DFF in counter into TFF, then there are only three states. 00->01->11
4,how to minimize noise using CMOS
5,setup time and hold time, what does skew influence setup time and hold time
6,What factors influence system frequency. I answered setup time.
7,asked my project, size of whole layout os SRAM and final project in 477.
8,how to decrease delay, I answered using larger size. update: increase I, such as size, Vdd, logical effort, decrease load. pipeline , parallel
