J'ai postulé en ligne. J'ai passé un entretien chez BITSILICA (Hyderâbâd) en juil. 2024
Entretien
basic and conceptual SV constraint and assertion questions.
verilog code of digital circuits along with testbench code.
uvm_scoreboard code templates.
APB FSM diagram explanation.
prime no constraint code and digital circuits using muxes.
Questions d'entretien [1]
Question 1
pass by value and pass by reference differences.
apb uvm driver code.
J'ai postulé en ligne. J'ai passé un entretien chez BITSILICA (Bangalore Rural) en mai 2023
Entretien
It was good, very social and very supportive. They actually tell the result very soon and schedule the next round according to your convenience. After every round they tell where we are lacking and how to answer the questions in a correct way.
J'ai postulé en ligne. Le processus a pris 3 jours. J'ai passé un entretien chez BITSILICA (Yavatmāl) en févr. 2022
Entretien
There are Two technical interview round and One HR round. The first technical interview is quite easy while the second seems to be tough. They offer an immediate joining letter after the HR round.
