J'ai postulé en ligne. J'ai passé un entretien chez Astranis en avr. 2021
Entretien
I applied on their main website, then got an email for an interview. They asked me two technical questions relating to digital logic (CDC) and verilog (writing synthesizable code based on some descriptions).
Questions d'entretien [1]
Question 1
Given you've generated an 80MHz, and 50MHz clock, how do you manage data crossing between these two clock domains?
