J'ai postulé via la recommandation d'un employé. Le processus a pris 5 jours. J'ai passé un entretien chez Arm (Bengaluru) en mars 2018
Entretien
Had 4 technical rounds + HR round.
1st round was by the team manager - mainly concentrated on my current project and verification skills
2nd rounds was taken by a staff engineer - c programs ( decimal to binary conversion, string palindrome) , fsm , logical questions , verilog based program.
3rd round was taken by senior engineer - verilog synthesis questions, blocking and blocking with eg, asynchronus and synchronus reset d flop
4th round was taken by the PE - this round was mostly to check how strong the candidate can analyze and verify - Verification strategies which included coverage assertions and other System verilog concepts.
5th round - HR round. Very meaningful round. Lunch was served. Totally a relaxing round.
Results were given in a day and turned out to be positive.
I had couple of offers with SanDisk , nvidia and Intel .
I opted ARM .
Thank you so much for taking time in writing a review about your experience at Arm. We are glad to know that you had a good interviewing experience. Thank you for choosing Arm and we look forward to joining us soon.
Autres retours d’entretien d’embauche pour un poste comme Verification Engineer chez Arm
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Arm (Manipal) en août 2025
Entretien
this is campus interview , starting asking me the reklevant coursework i have in my curriculum and breif intro about them ,like low power vlsi design -what they have taught us and asked about how dynamic,static ,short circuit power dissipation happens in an inverter . ,how to reduce them , power reduction techniques at logic level ,architecture level ,after this gone for verilog , basic bolcking and non blocking ,traffic signal using delay ,projects on digital design using verilog or system verilog
Questions d'entretien [1]
Question 1
1.difference between dynamic,static ,short circuit power diddipation ,where and how it happens ,how to reduce them
2. power reduction technoques at logic and architectute level
3. verilog
J'ai postulé en ligne. J'ai passé un entretien chez Arm (Austin, TX) en févr. 2025
Entretien
First round with manger of the team. It was way too theoretically technical. He asked questions like I was interviewing for his position. I am not expecting a call back from them.
Questions d'entretien [1]
Question 1
Question 1 : How do you verify a dual port memory
Question 2 : What is layered constraints
Question 3 : What is the use of UVM
Question 4 : What is config db
J'ai passé un entretien chez Arm (Cambridge, East of England, England)
Entretien
1 Round of digital inretview through hirevue, 90 minutes.
2 round if face to face interview, 2and half hour.
Quesntion include computer architecture and operating system
c and cpp code question
