J'ai postulé en ligne. J'ai passé un entretien chez AMD (Markham, ON) en févr. 2025
Entretien
I interviewed for the Design Verification Engineer Co-op position at AMD in Markham. The interview lasted 1 hour with no behavioral questions and it consisted of 4 technical questions.
Overall the experience was nice and the interviewers (I had two) were extremely helpful and provided useful hints if I was stuck.
Questions d'entretien [4]
Question 1
Given a function in C++, describe the intended purpose, what it returns, and fix the code so it actually returns what it is meant to return.
Given a truth table, draw the corresponding diagram. I was also asked questions on level triggered/edge triggered (which one is safer...stuff like that). Code the solution in Verilog/VHDL.
campus interview . 2 rounds, basic questions from STA , cmos, digital basics , verilog questions, verilog code for asynchronus d flipflop, blocking and non blocking statements, structure of 3 input OR gate, explain about static and dynamic power
1. HR Screen
2. Technical Round
The whole process was around 2 weeks.
You first get a call from the HR and then will answer questions.
If you are successful, you will book a time for a technical interview.
Questions d'entretien [1]
Question 1
Tell me the difference between combinational and sequential logic
I was not well prepared, It was basic q and a related to my current role and some basic OSI questions, Also interviewer was great he gave me time to understand the question and helped me with the hints
Questions d'entretien [1]
Question 1
A chip was given which performs (001)addition,(010) subtraction, (011)multiplication and division(100) on 8 bit value, it can store 20 operands at a time in a stack and 2 bits for error handling,
Arth overflow
Stack over
1.Questions was to find out end cases and possible errors and how can we handle it in verilog test benches?.
2. Also, How to write those test cases. ?
