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      Entretien pour FPGA Engineer

      18 févr. 2017
      Candidat à l'entretien anonyme
      Chicago, IL
      Aucune offre
      Expérience négative
      Entretien facile

      Candidature

      J'ai postulé via un recruteur. Le processus a pris 3 semaines. J'ai passé un entretien chez AKUNA CAPITAL (Chicago, IL) en juil. 2016

      Entretien

      It's probably the least professional interview process I've ever had. First round was online test from HackerRank where I was asked to complete choice questions within one hour. Questions were simple and fundamental hardware design questions most of which you should have known the answer at school. Second round was just another list of PRE-DESIGNED hardware design 101 questions. But instead of online, this time was phone interview by an FPGA engineer. Instead of asking design or anything ask you to think, it was nothing but plain knowledge question, e.g. what are the basic elements of FPGA, which is never heard of. Trust me, anyone with practical experience on FPGA design can answer those questions with beer in hand. And the most amazing thing is that they failed me on the 2nd round! Just shocked. So here comes why I think they are not professional. 1. The way they failed me is unheard of and I cannot imagine any company who values technology conduct such an interview. It's like hiring some Jeopardy contestant to create and innovate. 2. There was another HR talk somewhere between 1st and 2nd round. She actually asked me why I applied through recruiter and not directly from their website. Clearly she was upset about it from the tone she spoke. It felt like they were really concerned about commission for recruiters. 3. It took more than a week before my recruiter got any response from them. How long does it take to judge 20 choice questions online? I can understand they need to schedule multiple interviewees, but it's really disrespectful to just say nothing at all. Akuna basically wasted me quite some time to prepare and do the test/interview. Eventually I took offer from another much more competitive firm.

      Questions d'entretien [1]

      Question 1

      1st Rd: basic logic design, basic verilog/systemverilog syntax, setup/hold, etc. I think the only thing may not be on the book is timing result analysis which showed a few timing report and asked which one may have a better chance to fix, though it's still very simple. 2nd Rd: e.g. list FPGA elements. They are just so simple that you must have seen them in your daily work
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