Interviewed for FPGA Engineer. Had a practical test and then technical round.
Practical test was to write a VHDL code to divide a 160MHz clock to 40MHz, write a testbench and show the results. Have to use Xilinx ISE for coding and ModelSim for simulation.
Technical round had questions from digital design and hardware design in general.
Questions d'entretien [1]
Question 1
Simulation of Clock divider circuit - using Xilinx ISE and ModelSim
Various digital electronics questions - metastability etc.