2 rounds with engineers in team and with manager followed by HR round. digital questions, verilog, transistors sizing, setup, hold timing violation questions, clock skew, and logic optimization problems , noise margin questions.
Questions d'entretien [1]
Question 1
2 rounds with engineers in team and with manager followed by HR round. digital questions, verilog, transistors sizing, setup, hold timing violation questions, clock skew, and logic optimization problems , noise margin questions.