J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 1 semaine. J'ai passé un entretien chez AMD (Toronto, ON)
Entretien
2 hour long interview for the Video Codec Team at AMD Markham. The manager will bring in a design and verification lead from his/her team to ask you questions. You will answer using a whiteboard and a marker.
Questions d'entretien [12]
Question 1
Design an XOR logic circuit using only "AND" and "NOT" gates. (Hint : Just remember Demorgan's law to convert an "OR" gate to and "AND")
Draw a FSM (Either Moore/Mealy) to detect the pattern 10110. It should output 1 if it detects the pattern. (Make sure it also handles the case "10110110")
How will you verify the functionality of your Verilog code? How would the test best setup look like in UVM? Talk about UVM Sequencers, Drivers, Monitors and Scoreboards.
J'ai postulé en ligne. J'ai passé un entretien chez AMD
Entretien
Interviewers are very friendly, basic coding in Verilog and Python, questions on digital design concepts. Interviewers are interested in the details of past projects, in particular scripting, testing and debugging.
Le processus a pris 3 semaines. J'ai passé un entretien chez AMD (Sydney)
Entretien
The interview process involved an initial screening interview which was technical and after clearing it a follow up by a main technical interview was held which delved deep into core topics.
Questions d'entretien [1]
Question 1
Describe your project and your method of approach.
J'ai postulé en ligne. Le processus a pris 1 semaine. J'ai passé un entretien chez AMD en juin 2025
Entretien
1 round, 1 hour long technical interview with engineer. Questions about digital design, verilog, past experience/internships, etc. Introduction to product and internship responsibilities. Coding and block diagram drawing, as well as waveform analysis.