J'ai postulé via la recommandation d'un employé. J'ai passé un entretien chez Qualcomm (San Diego, CA) en mai 2025
Entretien
First i had a technical interview and then followed by HR round and then a panel round with 4 engineer it was a 1 on 1 interview.
basically the interview were schedule for 45 min with 1 Engineer. but mostly ended up for more than an 1hr.
J'ai postulé via un recruteur. J'ai passé un entretien chez Qualcomm en déc. 2025
Entretien
The interview process for an ASIC Design Verification (DV) Engineer typically includes resume screening, one or more technical phone or online interviews focusing on digital fundamentals, SystemVerilog, UVM, and debugging skills, followed by multiple in-depth technical and behavioral interview rounds assessing verification methodology, problem-solving ability, and teamwork.
Questions d'entretien [1]
Question 1
They mainly asked me to explain how to build and debug a UVM-based verification environment, including the roles of sequences, drivers, monitors, scoreboards, and how I handled a real bug or coverage issue during a project.
